// lvds_rx.v

// Generated using ACDS version 19.1 670

`timescale 1 ps / 1 ps
module lvds_rx (
		input  wire       rx_inclock,    //    rx_inclock.rx_inclock
		output wire       rx_outclock,   //   rx_outclock.rx_outclock
		input  wire       pll_areset,    //    pll_areset.pll_areset
		input  wire [0:0] rx_in,         //         rx_in.rx_in
		output wire [9:0] rx_out,        //        rx_out.rx_out
		output wire       rx_locked,     //     rx_locked.rx_locked
		input  wire       rx_data_align  // rx_data_align.rx_data_align
	);

	altera_soft_lvds_rx_C4QEN lvds_rx_inst (
		.rx_inclock            (rx_inclock),    //    rx_inclock.rx_inclock
		.rx_outclock           (rx_outclock),   //   rx_outclock.rx_outclock
		.pll_areset            (pll_areset),    //    pll_areset.pll_areset
		.rx_in                 (rx_in),         //         rx_in.rx_in
		.rx_out                (rx_out),        //        rx_out.rx_out
		.rx_locked             (rx_locked),     //     rx_locked.rx_locked
		.rx_data_align         (rx_data_align), // rx_data_align.rx_data_align
		.rx_channel_data_align (1'b0),          //   (terminated)
		.rx_cda_reset          (1'b0),          //   (terminated)
		.rx_data_align_reset   (1'b0)           //   (terminated)
	);

endmodule
